Given Max Baud Err = 0.75% and Max Timer Drift = 0% | |||||
Clock | Pre Scale |
RTCC Inc |
Max ISR Cycles |
ISR Rate |
Rates, per division w/ percent error
Timing period (min / max), per counter width w/ max drift |
---|---|---|---|---|---|
6.144Mhz | 1 | 255 | 255 | 24.094118Khz | ÷5=4800, ÷10=2400, ÷20=1200, ÷40=600, ÷80=300 |
6.144Mhz | 1 | 254 | 254 | 24.188976Khz | ÷81=300 |
6.144Mhz | 1 | 253 | 253 | 24.284585Khz | ÷81=300 |
6.144Mhz | 1 | 252 | 252 | 24.380952Khz | ÷81=300 |
6.144Mhz | 1 | 251 | 251 | 24.478088Khz | ÷41=600, ÷81=300+0.73%, ÷82=300 |
6.144Mhz | 1 | 250 | 250 | 24.576000Khz | ÷41=600, ÷82=300 |
6.144Mhz | 1 | 249 | 249 | 24.674699Khz | ÷41=600, ÷82=300 |
6.144Mhz | 1 | 248 | 248 | 24.774194Khz | ÷41=600+0.70%, ÷82=300+0.70%, ÷83=300-0.51% |
6.144Mhz | 1 | 247 | 247 | 24.874494Khz | ÷83=300 |
6.144Mhz | 1 | 246 | 246 | 24.975610Khz | ÷83=300 |
6.144Mhz | 1 | 245 | 245 | 25.077551Khz | ÷21=1200, ÷42=600, ÷83=300+0.71%, ÷84=300 |
6.144Mhz | 1 | 244 | 244 | 25.180328Khz | ÷21=1200, ÷42=600, ÷84=300 |
6.144Mhz | 1 | 243 | 243 | 25.283951Khz | ÷21=1200, ÷42=600, ÷84=300 |
6.144Mhz | 1 | 242 | 242 | 25.388430Khz | ÷21=1200+0.74%, ÷42=600+0.74%, ÷84=300+0.74%, ÷85=300 |
6.144Mhz | 1 | 241 | 241 | 25.493776Khz | ÷85=300 |
6.144Mhz | 1 | 240 | 240 | 25.600000Khz | ÷85=300 |
6.144Mhz | 1 | 239 | 239 | 25.707113Khz | ÷43=600, ÷86=300 |
6.144Mhz | 1 | 238 | 238 | 25.815126Khz | ÷43=600, ÷86=300 |
6.144Mhz | 1 | 237 | 237 | 25.924051Khz | ÷43=600, ÷86=300, ÷87=300-0.68% |
6.144Mhz | 1 | 236 | 236 | 26.033898Khz | ÷87=300 |