Peripheral circuit for Digital Clock

On this page, I will introduce a peripheral circuit
to use for "Ultra High Accuracy Digital Clock (Ver 2)".

I realize the following feature with this CPLD.
	SR flip-flop	This circuit is the flip-flop circuit which combined two NANDs. This circuit is used for the chattering prevention of the time setting mode selector switch and the setting switch in 0 seconds. There are 2 circuits.
	3-8 decoder	This circuit decodes the binary input of 3 bits to eight signals. This circuit is used for the selection of the digital display position.
	1/200000 frequency divider	This circuit makes the frequency of 1/200000 with the binary counter. This circuit is used to change a 10-MHz clock into the 50-Hz clock.

The CLPD which I used is XC9536-PC44.

SR flip-flop

The blue name is the inner signal name.

3-8 decoder

1/200000 frequency divider

It is separated by 1/100000 and 1/2 to make the duty of the output 50%.