Please title this page. (18Fmathstest

;=================================================================================== ;For PIC18 devices the following settings are available. ;=================================================================================== ; ;Oscillator Selection bits: ; CONFIG OSC = LP ;LP oscillator ; CONFIG OSC = XT ;XT oscillator CONFIG OSC = HS ;HS oscillator ; CONFIG OSC = RC ;External RC osc, CLKO function on RA6 ; CONFIG OSC = EC ;EC osc, CLKO function on RA6 ; CONFIG OSC = ECIO6 ;EC osc, port function on RA6 ; CONFIG OSC = HS ;HS osc, PLL disabled (Clock freq = 4 x FOSC1) ; CONFIG OSC = HSPLL ;HS osc, PLL enabled (Clock freq = 4 x FOSC1) ; CONFIG OSC = RCIO6 ;External RC osc, port on RA6 ; CONFIG OSC = INTIO67 ;Internal osc, port on RA6 and RA7 ; CONFIG OSC = INTIO7 ;Internal osc, CLKO on RA6, port on RA7 ; ;Fail-Safe Clock Monitor Enable bit: CONFIG FCMEN = OFF ;Fail-Safe Clock Monitor disabled ; CONFIG FCMEN = ON ;Fail-Safe Clock Monitor enabled ; ;Internal/External Oscillator Switchover bit: CONFIG IESO = OFF ;Oscillator Switchover mode disabled ; CONFIG IESO = ON ;Oscillator Switchover mode enabled ; ;Power-up Timer Enable bit: ; CONFIG PWRT = ON ;PWRT enabled CONFIG PWRT = OFF ;PWRT disabled ; ;Brown-out Reset Enable bits: CONFIG BOREN = OFF ;Brown-out Reset disabled in hw and sw ; CONFIG BOREN = ON ;Brown-out Reset enabled in sw (SBOREN is enabled) ; CONFIG BOREN = NOSLP ;Brown-out Reset enabled in hw (SBOREN is disabled) ; CONFIG BOREN = SBORDIS;Brown-out Reset enabled in hw (SBOREN is disabled) ; ;Brown-out Reset Voltage bits: ; CONFIG BORV = 0 ;Maximum setting CONFIG BORV = 1 ; CONFIG BORV = 2 ; CONFIG BORV = 3 ;Minimum setting ; ;Watchdog Timer Enable bit: CONFIG WDT = OFF ;WDT disabled (control is placed on the SWDTEN bit) ; CONFIG WDT = ON ;WDT enabled ; ;Watchdog Timer Postscale Select bits: ; CONFIG WDTPS = 1 ;1:1 ; CONFIG WDTPS = 2 ;1:2 ; CONFIG WDTPS = 4 ;1:4 ; CONFIG WDTPS = 8 ;1:8 ; CONFIG WDTPS = 16 ;1:16 ; CONFIG WDTPS = 32 ;1:32 ; CONFIG WDTPS = 64 ;1:64 CONFIG WDTPS = 128 ;1:128 ; CONFIG WDTPS = 256 ;1:256 ; CONFIG WDTPS = 512 ;1:512 ; CONFIG WDTPS = 1024 ;1:1024 ; CONFIG WDTPS = 2048 ;1:2048 ; CONFIG WDTPS = 4096 ;1:4096 ; CONFIG WDTPS = 8192 ;1:8192 ; CONFIG WDTPS = 16384 ;1:16384 ; CONFIG WDTPS = 32768 ;1:32768 ; ;MCLR Pin Enable bit: ; CONFIG MCLRE = OFF ;RE3 input pin enabled; MCLR disabled CONFIG MCLRE = ON ;MCLR pin enabled; RE3 input pin disabled ; ;Low-Power Timer1 Oscillator Enable bit: ; CONFIG LPT1OSC = OFF ;Timer1 configured for higher power operation CONFIG LPT1OSC = ON ;Timer1 configured for low-power operation ; ;PORTB A/D Enable bit: CONFIG PBADEN = OFF ;PORTB<4:0> configured as digital I/O on Reset ; PBADEN = ON ;PORTB<4:0> configured as analog input on Reset ; ;CCP2 MUX bit: CONFIG CCP2MX = PORTBE;CCP2 input/output is multiplexed with RB3 ; CONFIG CCP2MX = PORTC ;CCP2 input/output is multiplexed with RC1 ; ;Stack Full/Underflow Reset Enable bit: CONFIG STVREN = OFF ;Stack full/underflow will not cause Reset ; CONFIG STVREN = ON ;Stack full/underflow will cause Reset ; ;Single-Supply ICSP Enable bit: CONFIG LVP = OFF ;Single-Supply ICSP disabled ; CONFIG LVP = ON ;Single-Supply ICSP enabled ; ;Extended Instruction Set Enable bit: CONFIG XINST = OFF ;Instruction ext and Indexed Addressing disabled ; CONFIG XINST = ON ;Instruction ext and Indexed Addressing enabled ; ;Background Debugger Enable bit: CONFIG DEBUG = ON ;Debugger enabled, RB6 and RB7 dedicated to ICD ; DEBUG = OFF ;Debugger disabled, RB6 and RB7 are I/O pins ; ;Code Protection bit Block 0: ; CP0 = ON ;Block 0 (000800-001FFFh) code-protected CONFIG CP0 = OFF ;Block 0 (000800-001FFFh) not code-protected ; ;Code Protection bit Block 1: ; CP1 = ON ;Block 1 (002000-003FFFh) code-protected CONFIG CP1 = OFF ;Block 1 (002000-003FFFh) not code-protected ; ;Code Protection bit Block 2: ; CP2 = ON ;Block 2 (004000-005FFFh) code-protected CONFIG CP2 = OFF ;Block 2 (004000-005FFFh) not code-protected ; ;Code Protection bit Block 3: ; CP3 = ON ;Block 3 (006000-007FFFh) code-protected CONFIG CP3 = OFF ;Block 3 (006000-007FFFh) not code-protected ; ;Boot Block Code Protection bit: ; CPB = ON ;Boot block (000000-0007FFh) code-protected CONFIG CPB = OFF ;Boot block (000000-0007FFh) not code-protected ; ;Data EEPROM Code Protection bit: ; CONFIG CPD = ON ;Data EEPROM code-protected CONFIG CPD = OFF ;Data EEPROM not code-protected ; ;Write Protection bit Block 0: ; CONFIG WRT0 = ON ;Block 0 (000800-001FFFh) write-protected CONFIG WRT0 = OFF ;Block 0 (000800-001FFFh) not write-protected ; ;Write Protection bit Block 1: ; CONFIG WRT1 = ON ;Block 1 (002000-003FFFh) write-protected CONFIG WRT1 = OFF ;Block 1 (002000-003FFFh) not write-protected ; ;Write Protection bit Block 2: ; CONFIG WRT2 = ON ;Block 2 (004000-005FFFh) write-protected CONFIG WRT2 = OFF ;Block 2 (004000-005FFFh) not write-protected ; ;Write Protection bit Block 3: ; CONFIG WRT3 = ON ;Block 3 (006000-007FFFh) write-protected CONFIG WRT3 = OFF ;Block 3 (006000-007FFFh) not write-protected ; ;Boot Block Write Protection bit: ; CONFIG WRTB = ON ;Boot block (000000-0007FFh) write-protected CONFIG WRTB = OFF ;Boot block (000000-0007FFh) not write-protected ; ;Configuration Register Write Protection bit: ; CONFIG WRTC = ON ;Configuration registers (300000-3000FFh) write-protected CONFIG WRTC = OFF ;Configuration registers (300000-3000FFh) not write-protected ; ;Data EEPROM Write Protection bit: ; CONFIG WRTD = ON ;Data EEPROM write-protected CONFIG WRTD = OFF ;Data EEPROM not write-protected ; ;Table Read Protection bit Block 0: ; CONFIG EBTR0 = ON ;Block 0 (000800-001FFFh) other block table read protection CONFIG EBTR0 = OFF ;Block 0 (000800-001FFFh) no other block table read protection ; ;Table Read Protection bit Block 1: ; CONFIG EBTR1 = ON ;Block 1 (002000-003FFFh) other block table read protection CONFIG EBTR1 = OFF ;Block 1 (002000-003FFFh) no other block table read protection ; ;Table Read Protection bit Block 2: ; CONFIG EBTR2 = ON ;Block 2 (004000-005FFFh) other block table read protection CONFIG EBTR2 = OFF ;Block 2 (004000-005FFFh) no other block table read protection ; ;Table Read Protection bit Block 3: ; CONFIG EBTR3 = ON ;Block 3 (006000-007FFFh) other block table read protection CONFIG EBTR3 = OFF ;Block 3 (006000-007FFFh) no other block table read protection ; ;Boot Block Table Read Protection bit: ; CONFIG EBTRB = ON ;Boot block (000000-0007FFh) other block table read protection CONFIG EBTRB = OFF ;Boot block (000000-0007FFh) no other block table read protection ; ;========================================================================== ; ; Configuration Registers ; ; NAME Address ; CONFIG1H 300001h ; CONFIG2L 300002h ; CONFIG2H 300003h ; CONFIG3H 300005h ; CONFIG4L 300006h ; CONFIG5L 300008h ; CONFIG5H 300009h ; CONFIG6L 30000Ah ; CONFIG6H 30000Bh ; CONFIG7L 30000Ch ; CONFIG7H 30000Dh ; ;==========================================================================